The TXMC635 is a standard single-width Switched Mezzanine Card (XMC) compatible module providing a user configurable XC6SLX45T-2 or XC6SLX100T-2 AMD Spartan ™ 6 FPGA.
48 ESD-protected TTL lines provide a flexible digital interface. All I/O lines are individually programmable as input or output. Setting as input sets the I/O line to tri-state and could be used with on-board pull up also as open drain output. Each TTL I/O line has a pull resistor. The pull voltage level is selectable to be either +3.3V, +5V and additionally GND.
8 channels of 16 bit analog outputs allow software selectable output voltage ranges of ±10V, ±10.2564V or ±10.5263V. The output voltage range can be individually set per channel. The conversion time is at most 10 µs and the DAC outputs are routed via operational amplifier in order to protect DAC from damage.
32 ADC input channels can be software configured to operate in single-ended or differential mode with 16 input channels. Each of the 32 channels has a resolution of 16 bit and can work with up to 1 MSPS. The programmable gain amplifier is software configurable and allows a full-scale input voltage range of up to ±24.576V.
For customer specific I/O extension or inter-board communication, the TXMC635-xxR provides 64 FPGA I/Os lines on P14 and 3 FPGA Multi-Gigabit-Transceiver on P16. P14 I/O lines could be configured as 64 single ended LVCMOS33 or as 32 differential LVDS33 interface.
The User FPGA is connected to a 128 Mbytes, 16 bit wide DDR3 SDRAM. The SDRAM-interface uses a hardwired internal Memory Controller Block of the Spartan-6.
The User FPGA is configured by a platform SPI flash or via PCIe download. The flash device is in-system programmable. An in-circuit debugging option is available via a JTAG header for read back and real-time debugging of the FPGA design (using AMD ChipScope ™).
The direct configuration via PCIe of the User FPGA is realized by the Configuration FPGA. Configuration data is programmed via 32 bit transfer register to the User FPGA (AMD Spartan ™ 6). Data source are AMD ISE ™ binary files (.bit file or .bin file) which are generated by the ISE ™ Design Suite. These binary files consist of header, preamble and configuration data. Only configuration data must be transferred. See also the AMD User Guide (ug380) Spartan ™ 6 FPGA Configuration for more information about configuration details and configuration data file formats.
User applications for the TXMC635 with XC6SLX45T-2 FPGA can be developed using the design software ISE ™ Project Navigator (ISE) and Embedded Development Kit (EDK). IDE versions are 14.7. Licenses for both design tools are required.
TEWS offers a well-documented basic FPGA Example Application design. It includes an .ucf file with all necessary pin assignments and basic timing constraints. The example design covers the main functionalities of the TXMC635. It implements local bus interface to local bridge device, register mapping, DDR3 memory access and basic I/O. It comes as a AMD ISE ™ project with source code and as a ready-to-download bit stream.
